8 bit Single Cycle Processor in Verilog
Verilog Code For Single Cycle Processor
DATAPATH WITH CONTROLLER
PC VERILOG CODE
module ProgramCounter
(
input [4:0]d_in,
input reset, clk,
output reg [4:0] d_out
);
always @(posedge clk)
if (reset)
d_out <= 5b00000;
else
d_out <= d_in;
endmodule
AC VERILOG CODE
module Accumulator
(input [7:0] d_in,
input load, clk,
output reg [7:0] d_out
);
always @(posedge clk)
if (load)
d_out <= d_in;
initial
d_out=8h00;
endmodule
ALU VERILOG CODE
module ALU
(
input [7:0]a, input [7:0]b,input [2:0]opcode,
output reg [7:0]alu_out
);
always @(opcode,a,b)
case(opcode)
3b000:alu_out = a + b;
3b001:alu_out = a - b;
3b010:alu_out = a&b;
3b011:alu_out = a|b;
3b100:alu_out = ~b;
3b101:alu_out = a^b;
3b110:alu_out = a~^b;
default:alu_out = 0;
endcase
endmodule
ADDER VERILOG CODE
module CounterIncrement
(
input [4:0]a, input [4:0]b,
output[4:0] adder_out
);
assign adder_out = a + b;
endmodule
-
MUX-1 VERILOG CODE
module Mux2to1_6Bit
(
input [4:0] i0, i1,input sel,
output[4:0] mux_out
);
assign mux_out = sel ? i1 : i0;
endmodule
MUX-2 VERILOG CODE
module Mux2to1_8Bit
(
input [7:0]i0,i1,input sel,
output [7:0]mux_out
);
assign mux_out =sel?i1:i0;
endmodule
CONTROLLER VERILOG CODE
module Controller(
input [2:0] opcode,
output reg rd_mem,wr_mem,ac_src,ld_ac,pc_src,jmp_uncond);
always @(opcode)
begin
rd_mem = 1b0;
wr_mem = 1b0;
ac_src = 1b0;
pc_src = 1b0;
ld_ac = 1b0;
jmp_uncond=1b0;
case (opcode)
3b000: //load accumulator from memory
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;
end
-
3b001:
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;//SUBTRACT
end
3b010:
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;//AND
end
3b011:
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;//OR
end
3b100:
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;//NOT
end
3b101:
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;//XOR
end
3b110:
begin
rd_mem = 1b1;
wr_mem = 1b0;
ld_ac = 1b1;
ac_src = 1b0;//XNOR
end
3b111:
begin
rd_mem = 1b0;
wr_mem = 1b0;
ld_ac = 1b0;
ac_src = 1b0;
pc_src=1b1;
jmp_uncond=1b1;//JUMP
end
default:
begin
rd_mem = 1b0;
wr_mem = 1b0;
ac_src = 1b0;
pc_src = 1b0;
ld_ac = 1b0;
end
endcase //end case
end //end always
endmodule
DATA MEMORY VERILOG CODE
module DataMemory (
input rd, wr,
input [4:0] abus,
input [7:0] in_dbus,
output reg [7:0] out_dbus);
reg [7:0] dm_array [0:31];
always @(rd,abus)
begin
if (rd)
out_dbus = dm_array [abus];
end
always @(wr,in_dbus) //always @(wr or abus or in_dbus)
begin
if (wr)
dm_array [abus] = in_dbus;
end
-
initial
begin
dm_array[0] = 8h01;
dm_array[1] = 8h02;
dm_array[2] = 8h03;
dm_array[3] = 8h04;
dm_array[4] = 8h05;
end
endmodule
INSTRUCTION MEMORY VERILOG CODE
module InstructionMemory (input [4:0] abus, output reg [7:0] dbus);
reg [7:0] im_array [0:12];
always @(abus)
dbus = im_array [abus];
initial
begin
im_array[0]= 8h00; // Initialize Accumulator with 0 and do addition with content of DataMemory at address 0.
im_array[1]= 8h21; // Subtract content of accumulator with content of DataMemory at address 1.
im_array[2]= 8h42; // Logical AND of accumulator with content of DataMemory at address 2.
im_array[3]= 8h63; // Logical OR of accumulator with content of DataMemory at address 3.
im_array[4]= 8h84; // Logical NOT of accumulator with content of DataMemory at address 4.
im_array[5]= 8hA4; // Logical XOR of accumulator with content of DataMemory at address 4.
im_array[6]= 8hC4; // Logical XNOR of accumulator with content of DataMemory at address 4.
im_array[7]= 8hEA; // Unconditional Jump to 01010 address of Instruction memory.
im_array[10]= 8h00; // Addition with content of DataMemory at address 0.
im_array[11]= 8hE0; // Unconditional Jump to 00000 address of Instruction memory.
end
endmodule
-
DATAPATH MEMORY VERILOG CODE
module DataPath (
input reset,ld_ac, ac_src, pc_src, clk,
output [2:0] opcode,
output [4:0] im_abus,
input [7:0] im_dbus,
output [4:0] dm_abus,
output [7:0] dm_in_dbus,
input [7:0] dm_out_dbus,
output [7:0] ac_out,alu_out);
//wire [7:0] ac_out,alu_out,mux2_out;
wire [7:0]mux2_out;
wire [4:0] pc_out, adder_out,mux1_out;
ProgramCounter pc(.d_in(mux1_out),.reset(reset),.clk(clk),.d_out(pc_out)); //instantiation
of all module
CounterIncrement adder(.a(pc_out),.b(5b00001),.adder_out(adder_out));
Mux2to1_6Bit mux1(.i0(adder_out),.i1(im_dbus[4:0]),.sel(pc_src),.mux_out(mux1_out));
Accumulator ac(.d_in(mux2_out),.load(ld_ac),.clk(clk),.d_out(ac_out));
ALU alu(.a(ac_out),.b(dm_out_dbus),.opcode(opcode),.alu_out